This invention relates to fine line patterning of semiconductor integrated circuits, and more particularly to a method of forming minute patterns in silicon by dry etching, such as by means of a chemical reactant in plasma form.
As the line geometry of semiconductor integrated circuit devices becomes smaller, there is a trend toward utilizing plasma dry etching processes instead of wet chemical etching processes. For more precise line width control the etching process should be anisotropic. In anisotropic etching of silicon, for example, the process of etching proceeds in depth only, in a vertical direction relative to the horizontal surface of the silicon wafer. In isotropic etching, in contrast, the silicon material etches both laterally and vertically, with the lateral component of etching producing an undercutting of the silicon surface beneath the masking material.
While anisotropic etching is preferred for obtaining more precise line width control, the sharp profile associated with the abrupt vertical etched wall which makes a 90.degree. angle with the horizontal silicon surface gives rise to many severe manufacturing problems, such as those associated with step coverage, oxide overhang, residual ribbon formation, and photoresist bridging, to mention a few. These problems can be alleviated to a considerable extent by shaping the edge profile of the etched silicon so that it has a flat, inclined slope considerably less than 90.degree. relative to the horizontal silicon surface.